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Alif Semiconductor /AE302F80F5582LE_CM55_HE_View /I3C /I3C_SCL_LOW_MST_EXT_TIMEOUT

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Interpret as I3C_SCL_LOW_MST_EXT_TIMEOUT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCL_LOW_MST_TIMEOUT_COUNT

Description

SCL Low Master Extended Timeout Register

Fields

SCL_LOW_MST_TIMEOUT_COUNT

This count defines the number of CORE_CLK periods to count for generation of the SCL low bus reset pattern.

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THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data